`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2023/11/28 13:57:17
// Design Name: 
// Module Name: TEST
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////

`timescale 1ns / 1ps
 
module TEST;
 
//module CPU(Clk,Reset,Inst,Qb,Qa,Addr
 
//,Result,PCadd4,EXTIMM,InstL2,EXTIMML2,D,Y,Dout,mux4x32_2,R,
 
//Z,Regrt,Se,Wreg,Aluqb,Reg2reg,Cout,Wmem,
 
//Aluc,Pcsrc,Wr
 
//);
 
 
 
reg Clk,Reset;
 
wire [31:0] Inst,Qb,Qa,Addr;
 
 
 
wire [31:0]Result,PCadd4,EXTIMM,InstL2,EXTIMML2,D,Y,Dout,mux4x32_2,R;
 
wire Z,Regrt,Se,Wreg,Aluqb,Reg2reg,Cout,Wmem;
 
wire [1:0]Aluc,Pcsrc;
 
wire [4:0]Wr;
 
 
 
CPU test(
 
.Clk(Clk),
 
.Reset(Reset),
 
.Inst(Inst),
 
.Qa(Qa),
 
.Qb(Qb),
 
.Addr(Addr),
 
.Result(Result),
 
.PCadd4(PCadd4),
 
.EXTIMM(EXTIMM),
 
.InstL2(InstL2),
 
.EXTIMML2(EXTIMML2),
 
.D(D),
 
.Y(Y),
 
.Dout(Dout),
 
.mux4x32_2(mux4x32_2),
 
.R(R),
 
.Z(Z),
 
.Regrt(Regrt),
 
.Se(Se),
 
.Wreg(Wreg),
 
.Aluqb(Aluqb),
 
.Reg2reg(Reg2reg),
 
.Cout(Cout),
 
.Wmem(Wmem),
 
.Aluc(Aluc),
 
.Pcsrc(Pcsrc),
 
.Wr(Wr)
 
);
 
    initial begin
 
        Clk=0;Reset=0;
 
        #10;
 
        Clk=1;Reset=0;
 
        #10;
 
        Reset=1;
 
        Clk=0;
 
        forever #20 Clk=~Clk;
 
    end
 
endmodule

